Pipelining -Mips instructions -

i have confused using pipelining in mips instruction. great. in advance.

what data dependency in next 2 codes? of them can solved using stall (bubble) or forwarding. can use shape 1 convenience.

          shape 1:             if-id-ex-mem-wb 

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explanation:

if=instruction fetch  id=instruction decode register fetch  ex=execute  mem=memory access  wb=write  

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code 1:

add $3,$4,$2  sub $5,$3,$1  lw  $6,200($5)  sw  $6,200($2)  lw  $6,200($3)  add $7,$4,$6 

code 2:

add $3,$4,$2  sub $5,$3,$1  lw $6,200($3)  add $7,$3,$6 

(sorry bad post,but can't yet post image)

thanks.

let's see first one:

add $3,$4,$2    sub $5,$3,$1 

the result add used in sub, therefore there data hazard. have insert amount of nop stages resolve it. assuming instructions take 5 cycles, insert 3 nops , we're done.

add $3,$4,$2  if  id  ex mem  wb    sub $5,$3,$1     nop nop nop  if  id  ex mem  wb 

we can subsequent instructions. instructions produce new values in ex , mem stages. values not written register until wb stage (for learning purposes, let's assume that's true). since registers read in id stage, leaves window of 3 cycles old incorrect values "flowing" through pipeline. forwarding can cure problem in our case above - forward result add:ex sub:id.

hope helps.